Re: Special XOR for half-adder and full-adder

Posted by jonk on Mar 02, 2016; 9:03pm
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/Special-XOR-for-half-adder-and-full-adder-tp4029600p4029610.html

Hehe. I really LOVE this whole process. (Did chipset testing, which also involved lots of FPGA programming, for Intel circa the BX chipset and the Pentium Pro and Pentium II days. And worked on CPU emulation using a huge box literally FILLED with Xilinx FPGAs all eventually hooked up to a tiny little CPU socket connector!)

For those interested in learning, from scratch, about both VHDL and verilog and who may also like to see side-by-side comparisons, as well as some interesting and very useful implementations that may be useful in moving towards a CPU design, I also enjoyed Mr. Smith's "Hdl Chip Design: A Practical Guide for Designing, Synthesizing & Simulating Asics & Fpgas Using Vhdl or Verilog" book. He came to the US from Britain and settled first in Alabama, I think. (I had occasion to talk with him on the phone for a while when he first arrived here in the US late in the 1990's.) It is very handy to see the left page showing something in VHDL and the right page showing the same something done up in verilog. And the book is for newbies. So very nice in that regard.

I also like and have these:

"Microprocessor Design Using Verilog HDL" by Monte Dalrymple.

"VHDL: A Starter's Guide, 2nd edition" by Sudhakar Yalamanchili

"RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability" by Pong P. Chu.

They are all good, I think.

Thanks so much for the links to some interesting, additional threads to look over.

Jon


P.S. I really DO wish the simulator had included a nice "for" to help reduce the number of lines I have to type in. Oh, well.