Re: Special XOR for half-adder and full-adder

Posted by jonk on Mar 04, 2016; 6:45am
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/Special-XOR-for-half-adder-and-full-adder-tp4029600p4029621.html

The bare XOR, as you show it, has a few problems. The voltage swing at the output isn't full-swing and it has a very limited driving capability and it doesn't work so well at lower voltage rails. There are some different arrangements with better drive, at the cost of higher power.

Also, XOR _and_ XNOR are often simultaneously needed in compressor cells used in multipliers, for example. So there is a need for something that achieves both at the same time and where there isn't a difference in propagation delays for the two outputs, as well (which would obviously exist if you used an inverter at the output to get the extra signal.)

There's a nice 8-transistor XOR cell which provides good drive and works well with low voltage rails. But the use of two inverters at the input increases its power consumption. And using an inverter also at its ouput adds still more power consumption (plus a largish skew between the XOR and XNOR output attending the addition of the inverter.)

Some interesting arrangements have been used to provide both XOR and XNOR without skew and workable at low Vcc voltages, have high drive capability, and handle high relative noise levels. Additions using dual feedback arrangements are quite noise tolerant and also provide a significant improvement in the power-delay product.

Holes, as you say, have quite a bit lower mobility. I believe I also learned that the ratio is about 3:1, but I think modern devices and doping level differences allow perhaps closer to 2:1, now. If my memory is right about that, the input loading difference between a NAND (parallel P-MOS on top, series N-MOS on bottom) vs a NOR (parallel N-MOS on bottom, series P-MOS on top) is about 4:5. Assuming a straight inverter loads as "3", given a double-sized P-MOS and a single-sized N-MOS both driven by the input, then a NAND input must drive one of a pair of double-sized N-MOS on the bottom (as they are in series) and a usual double-sized P-MOS on top, for a load of "4". And a NOR must used a quad-sized P-MOS on top (as they are in series there) and a single-sized N-MOS on bottom, for a load of "5". Hence the 4:5 comparison between them, input loading wise. (Output drives are the same.) Of course, if it is still 3:1 for P vs N, then the above calculations will be changed appropriately. (Loading is a reasonable analog for propagation delay.)

I never did that much with carry look-ahead. I used the slices available in FPGAs, so it wasn't something I needed to learn more about. I'm still reading through those pages you linked, though. I'd like to fully understand both the mathematics as well as the specific implementations you mentioned. In particular, though, I'm curious about modifying your PFA concept to use the /carry output of a 4-NAND XOR instead of using a separate AND gate to generate the G signal. In short, I'd like to see the logic using a /G output, instead of the G output. I'm going to enjoy playing a little bit.