Re: Understanding DFF behaviour

Posted by jbloggz on Apr 18, 2016; 10:15am
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/Understanding-DFF-behaviour-tp4029740p4029741.html

OK, so I think I've found the answer to my question. After looking at the Logism diagram here, I see that when the clock signal is put into the master flip flop, it is split into 2 signals which both go into an AND gate, however one of those signals is put through a YES gate then a NOT gate before the AND gate.

This means that the output of the AND gate is always 0 (because the two signals going into the AND gate will be opposite), except for a very small time after the rising edge the clock. This is due to the high signal from the clock arriving at the AND gate slightly before the inverted signal, which must first travel through 2 other gates. So for this brief period, there is 2 high signals at the AND gate and it outputs HIGH. So the master flip flop can only be changed during this short time period.

It doesn't seem like the YES gate is necessary to me, however perhaps it is needed to increase the propagation delay so that the AND gate will output high for a long enough period? Is there any other reason to include it?

I think this is a very elegant and am quite impressed by it. I am also happy that I now understand exactly how the DFF in the hardware simulator can be built. (And I also now understand why it is not possible to create the DFF in the hardware simulator using HDL, since it doesn't deal with things like propagation delay).

I'd appreciate if anyone who knows more about this stuff than me can let me know if this all makes sense....