Re: Confusion about ticks and tocks

Posted by WBahn on Feb 03, 2019; 4:40am
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/Confusion-about-ticks-and-tocks-tp4032821p4032828.html

It really doesn't matter and is largely indiscernible.

The problem with simulating circuits whose outputs are fed back to the inputs is that they can oscillate. Imagine a NOT gate whose output is connected to the input. If the input is LO, then the output goes HI, taking the input HI, which takes the output LO, which takes the input LO, which then starts the cycle all over again. In fact, this is basically how they measure the intrinsic speed of a digital technology -- put a large, odd number of inverters configured in a ring and measure the frequency of oscillation. Not surprisingly, this is known as a ring oscillator.

But now imagine we take our NOT gate and connect the output to the input of a DFF and then the output of the DFF back to the input of the NOT gate. What we probably expect to have happen is that the output of the DFF will be a square wave at half the frequency of the clock signal. But, if the DFF is fast enough, the data from the input can make it to the output quick enough so that it makes it back through the NOT gate and back to the input of the DFF while it is still sensitive to the input level. This could continue for several cycles until enough time has passed since the clock signal changed to make the DFF insensitive to the inputs.

I once killed a chip design for exactly this reason when we ported it to a faster technology on a real tight schedule and I didn't do the detailed simulations I should have to verify that this wasn't a problem.

The basic issue is one which the simple logic simulator used in Nand2Tetris can't deal with because it would have to have timing information about all of the gates being simulated. But that's pure overkill. So instead, they break the clock cycle into two pieces. On one piece the input state of each DFF is captured and stored, but the output state is left alone. On the other piece the output state of each DFF is updated and changes to the combinatorial parts of the circuit are determined, but the inputs to the DFFs can not affect their outputs.

This same approach is often used in hardware and is called a master-slave configuration. The master is sensitive to changes on one polarity of the clock and the slave is sensitive to the other. The inputs drive the master, the master drives the slave, and the slave drives the outputs.

The simulator here could have just had 'ticks' in the control file, one per clock cycle, with the simulator automatically dealing with the issue. But they chose to have the control file provide both.

You can either think of the tick as the high side of the clock and the tock as the low side, or the tick as the rising edge and the tock as the falling edge.