Re: Confusion about ticks and tocks

Posted by WBahn on Feb 04, 2019; 12:27am
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/Confusion-about-ticks-and-tocks-tp4032821p4032832.html

There are several different types of latches and flip flops, so no explanation can be too detailed unless it is restricted to a specific circuit.

Most flip flops are "edge-triggered" (usually on the rising edge, so that's what we'll assume). While the clock is low, the input section of the circuit is sensitive to changes in the input(s). As the clock rises this part of the flip-flop circuit locks in the value and quickly becomes insensitive to further changes on the inputs. In order for this work correctly, the inputs must remain constant at valid logic levels from a short time before the clock starts rising until a short time after it stops rising. These are known as the "setup" and "hold" time requirements. For convenience and consistency, these times are usually referred to the moment the clock signal has risen halfway from LO to HI. At the same time, the changes are propagated to the output. The time it takes for this to happen from when the clock changes is known as the "propagation delay". As long as the propagation delay is longer than the hold time, the changed output can't make it back to the input in time for it to further affect the output on that clock cycle. This all happens on the rising edge of the clock. On the falling edge the internal circuits essentially rearm themselves so as to be ready for the next rising edge.

And, yes, the clock doesn't transition instantly -- it takes time and this is known as the clock transition time. For most purposes, this doesn't matter to the circuit designer using the chip as long as they are careful to be sure that their clock signal meets the minimum and maximum transition times dictated by the chip's specifications.