Re: Confusion about ticks and tocks

Posted by WBahn on Feb 04, 2019; 7:27pm
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/Confusion-about-ticks-and-tocks-tp4032821p4032835.html

If I tell you that the propagation delay from clock to output is 30 ns, what does that mean. It's 30 ns from what event to what event? It's not good enough to say that it's from the clock rising edge to the change in the output, because both of those take a certain amount of time to happen, so we need to agree on when, exactly, to start measuring the time and when, exactly, to stop measuring it. We can't use either the start or the top of the transition because detecting the start time of a change would be hopelessly mired down in the noise that is always present. Detecting when the change stops is even worse because there is usually some kind of exponential asymptotic behavior as it settles into the noise at the final voltage. So, instead, most manufactures specify that the propagation time is measured starting from when the clock signal is halfway from LO to HI and stops when the changing output is halfway from its original level to its final level.

There's a definite arbitrariness to this choice -- there's nothing magical about the 50% level. It's just something that is very easy to specify and measure and, over the years, has become the defacto standard.

One thing that you need to keep in mind is that these are not hard numbers, meaning that the manufacturer is not saying that it WILL take EXACTLY 30 ns from the time the clock reaches 50% for the output to reach 50%, they are only saying that it will take NO MORE than 30 ns for that to happen. So they just have to come up with a specification that they know their chips can meet and they can (and do) pad it by making sure that their chips almost always comfortably beat their own specs.

For parts that have a positive hold time requirement, they will also usually spec a minimum propagation delay precisely to prevent the oscillation I've been talking about. But there's a common trick that is played -- the inputs are intentionally delayed (resulting in a larger setup time) so that the delay is longer than the hold time. Since all of this is internal to the chip, the end result is actually a negative hold time making it so that the chip cannot oscillate even if the propagation delay through the chip from clock to output were zero. You can tell when this has been done because the specs will usually give a hold time of zero (even though strictly speaking it is a negative number, but that would just confuse people).