Posted by
WBahn on
Feb 06, 2019; 6:04am
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/Confusion-about-ticks-and-tocks-tp4032821p4032843.html
Greemngreek wrote
Here's my final understanding of the working of a DFF:
The input satisfies setup requirements (and hold requirements later), gets cemented during the rising edge of the clock, gets propagated to the output after a delay, the falling edge prepares the DFF for a new input,
Good thus far.
<quote>
the output (in the new cycle) is not equal to the previous input (just before the rising edge of the previous cycle) till the rising edge of the clock cycle.
Hard to tell since I can't determine where you are defining the rising edge of a clock cycle to be. Is the rising edge at the beginning or the end of the clock cycle?
As I described earlier, for MOST DFF circuits (not all), the output shortly after the rising edge is equal to what the input was shortly before that same rising edge. Once that happens, the output will not change until just after the next rising edge of the clock; but the input can change all it wants to and is simply ignored. If for no other reason, that's why a claim that out(t) = in (t-1) can't always be true for a continuous variable t. We have to understand what information that equation is telling us. It is telling us that the output just after the rising clock edge (no later than the propagation delay from from clock edge to output) is equal to the value that was at the input just before that same rising clock edge (during the setup and hold time for the input relative to the clock -- if the data was not stable and valid during that entire time period, all bets are off).
Here are my concluding doubts:
Is the output at the end of the propagation delay equal to the input before the rising edge?
Yes, provided the setup and hold time requirements were satisfied.
Why isn't the output from the end of the propagation delay to the rising edge of the next clock cycle consistently equal to the input before rising edge of the current cycle? Is the output inconsistent?
It's not the output that can change. It's the input. The input could have changed a hundred times during both the prior clock cycle and the new clock cycle, but the output only gets to change at most once per clock cycle. The DFF samples the input during that tiny brief window in the vicinity of the rising clock edge and makes it's decision about what the output will be for the entire next clock cycle (after the prop delay, of course) and it ignores the input signal at all other times.
If the input is constant at a valid logic level from the beginning to the end of the clock, will the output then follow out(t-1) = in(t)?
No, but in well-designed system it will be close.
This equation, to be interpreted strictly, requires that the output waveform be an exact copy of the input waveform shifted by 1 time unit to the right (and we are assuming that the clock period is exactly one time unit, whatever that may be).
The only way that this equation will be true is if the input waveform changes occur exactly one clock cycle before the output changes occur. Since the output changes occur slightly after the rising clock edge, the input changes would have to occur then, as well (except on the prior edge). If the input for one DFF is coming from the output of another, then this will be a good approximation and we can live with it in most cases. But if the input is coming from something else, such as an external device, then who knows? For instance, a common technique to bring in external data is to sample it at the falling clock edge (usually twice, depending on the nature of the data signal).