Last 4 Mulit-way Mulit-bit gates

Posted by ouverson on
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/Last-4-Mulit-way-Mulit-bit-gates-tp4033146.html

I'm under the impression that sub-busing is the linchpin to understanding how to tackle multi-way, multi-bit gates: such as Mux4Way16.

I started playing with an implementation that piped the output of one Mux16 into another Mux16, similarly to how I implemented the Or8Way; however, that brought to the surface another challenge: how to manage sel[2]. Even if I pipe the output of one Mux16 into another I still have to manage sel[0] and sel[1]. At that point the arrangement of Mux16s got all arbitrary, and I felt this was a dead-end.

Please help me understand how to leverage sub-busing to solve implementation. If it's not about sub-busing please point me to the correct topics, concepts, techniques, etc.

Thank you.

P.S.

In the "HDL Survival Guide", under section "Bit Numbering and Bus Syntax":

"Hardware bits are numbered from right to left, starting with 0. When a bus is carrying a number, bit n is the bit with weight 2n. (2 to the nth power)

For example, when the book says sel=110, it means that a bus named sel receives the inputs 110. That means sel[2]=1, sel[1]=1 and sel[0]=0"

Not sure what the highlighted text means. I'm trying to map the sentence with the example that follows and don't see the connection.