Re: I'm working on my last chip in chapter/week 3: the PC chip

Posted by ouverson on Jul 16, 2019; 12:20pm
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/I-m-working-on-my-last-chip-in-chapter-week-3-the-PC-chip-tp4033386p4033391.html

I'm having issues with my inc implementation. I've tried putting Inc16 in front and behind Register.

Interestingly, both scenarios (placing Inc16 before and after Register) failed at tick (1+ and 3+). I wouldn't think that the failure would happen at tock when the output happens and not when components are "loaded".

Appreciate a gentle nudge :)

https://www.dropbox.com/s/a98x9kbo7sy1o2j/PC-implementation.png?dl=0

Regarding the question you ask upon my original post:

WBahn wrote

Your reset=0, load=1, and inc=1.

What does the chip specification say should happen under those conditions?

I would say the answer would be: load in at tick and output in at tock.