Re: I'm working on my last chip in chapter/week 3: the PC chip

Posted by WBahn on Jul 18, 2019; 7:12pm
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/I-m-working-on-my-last-chip-in-chapter-week-3-the-PC-chip-tp4033386p4033398.html

You have the right idea.

Keep in mind that you have some options in that you control which signals go to which input, and by making different assignments (there are 24 possibilities) you get different logic, so some will be "better" than others.

I don't think the one you've chosen is all the bad -- it may or may not be the "best".

Consider your sel[1] signal. You have six terms with three signals in each term. If you look at it closely, you can do it with a single two-input logic gate. Your sel[0] signal also reduces down quite a bit, but not as much.