Re: I'm working on my last chip in chapter/week 3: the PC chip

Posted by ouverson on Jul 18, 2019; 10:30pm
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/I-m-working-on-my-last-chip-in-chapter-week-3-the-PC-chip-tp4033386p4033399.html

Are you saying that my 6-term canonical expression for sel[1] can be reduced to a single two-input logic gate?

I know there are algebraic rules to assist in reducing canonical expressions. Can you please share how you would tackle this job.