Re: I'm working on my last chip in chapter/week 3: the PC chip

Posted by WBahn on Jul 19, 2019; 6:50pm
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/I-m-working-on-my-last-chip-in-chapter-week-3-the-PC-chip-tp4033386p4033400.html

ouverson wrote

Are you saying that my 6-term canonical expression for sel[1] can be reduced to a single two-input logic gate?

I know there are algebraic rules to assist in reducing canonical expressions. Can you please share how you would tackle this job.

There are several ways to do it. In this case, just looking at the truth table reveals the logic -- but it takes a bit of experience to spot it. Since I've told you that it can be done with a single two-input OR gate, go through and consider all three possibilities. After you find the one that works, look at the truth table and see if you can spot the pattern that makes it fairly evident that that's the logic that is needed.

A more formal way of doing it is using Karnaugh maps, which are a visual technique for minimizing logic equations (where "minimal" is constrained by being in one of two standard forms).

And, yes, you can do it directly from your logic equation; but this is a bit cumbersome and relies on some level of skill and practice in Boolean algebra, which is both simpler and harder than normal algebra.

Consider part of your sel[1] expression:

R'LI' + R'LI

This can be written as

R'L(I' + I)

But anything OR'ed with its complement is always True (or 1), so this becomes

R'L(1)

Now, anything AND'ed with 1 is just itself, leaving us with

R'LI' + R'LI = R'L

See if you can work it from there. Get as far as you can and post what you've got and we'll push through whatever roadblock you come up against.