Re: I'm working on my last chip in chapter/week 3: the PC chip

Posted by WBahn on Jul 19, 2019; 8:29pm
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/I-m-working-on-my-last-chip-in-chapter-week-3-the-PC-chip-tp4033386p4033402.html

ouverson wrote

When you say, "... three possibilities" what are you referencing? The only thing that stands out to me is the order of reset, load, and inc columns; if that's the case, how would that change the canonical expression? There would still be 6 terms with exactly the same values per term (just rearranged values.)

I keep hearing about Karnaugh maps; I suppose I should investigate.

In the meantime, I'll work on reducing my sel[1] expression, with the goal of getting to the 2 input OR gate.

Really appreciate your time. Thanks.

The three possibilities refers to the three ways to combined three signals using a single two-input OR gate.

If I have signals A, B, and C. Then the only options I have under that constraint are:

A Or B
A Or C
B Or C

Notice that this means that, whatever I do, there is one signal that I am ignoring completely. That means that, given the values of the two that I'm not ignoring, that I know the value that output needs to be regardless of what the value of the third happens to be. Do you see that behavior in your truth table?