Re: I'm working on my last chip in chapter/week 3: the PC chip

Posted by WBahn on Jul 22, 2019; 3:36am
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/I-m-working-on-my-last-chip-in-chapter-week-3-the-PC-chip-tp4033386p4033410.html

In general it's preferred that you not edit posts in such a way that it completely changes the content -- forums are archival by nature and so edits should be confined to fixing typos or clarifying content. It's better to just make a new post. Also, editing a post does not result in people being notified of the change, so people following the thread will have no idea that there is new stuff -- I just happen to notice that there seemed to be something new as I was checking something else.

Your solution for sel[0] will work, but it can be simplified further. What would happen if you eliminated the requirement that reset be 0 in order to cover the one case that is not covered by reset = 1? It would result in two rows being a 1, the one that you are trying to cover (001) and one that is already covered (101). But there's no harm in covering rows multiple ways so the fact that (101) also happens to be covered by the other signal going into the Or gate doesn't matter. That one change will eliminate a Not gate and an And gate.

To improve on this requires taking the internals of the gates into account -- something that the Nand-2-Tetris projects makes difficult because of the focus on building everything from Nand gates.

To give you some idea of the difference this can make, in CMOS your current solution would use 22 transistors and the delay from input to output is seven times the time it takes to go through a single NAND gate (a unit of time called a "gate delay"). If we just make the change I talked about above, that reduces it to 14 transistors and five gate delays. If we take the internals into account, we can get it down to 12 transistors and only three gate delays. Using a direct CMOS implementation (instead of building it up using discrete logic gates) we can get it down to 10 transistors and just two gate delays.