HackCPU and DATA bus architecture

Posted by clinden on
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/HackCPU-and-DATA-bus-architecture-tp4034390.html

Hi,

I grew up with Z80 CPUs and Assembler. I worked on a Amstrad CPC and as any other computer I could get my hand on it actually have a data bus instead of a read and write bus to memory.

I now have issues:
1. In real world no RAM with separated input and output exist. They have been optimized to have a bus and either output data or input data from that bus.
2. The CPU and all other Chips that require data transfer are all connected to the same data bus and specific logic regulates who reads and who writes on the bus to avoid conflicts and jams. More complicated designs will get more and more complicated because of this design.

So my questions are:
1. What was the design principles to not design a bus structure.
2. How could I build that in HDL if at all? A RAM chip having input and output data lines shared with an additional read/write line would do it, but I would need to define a chip where input line and output lines are the same. (my fear is I will never be able to, because the limit of input cannot be output at the same time in the HDL simluator you used).