Re: Simplest possible ALU implementation using only previously-defined chips?

Posted by WBahn on
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/Simplest-possible-ALU-implementation-using-only-previously-defined-chips-tp4034757p4034980.html

SirGouki wrote

I know this is outside the scope of nand2tetris, but you can easily implement AND with 2 transistors, and not with 1 (making nand 3 transistors since it is not(and)).

Is there a reason why nand would use 4 transistors instead of 3?

I've realised, by looking it up, that you can also implement nand itself with 2 transistors, but I suspect this circuit diagram to be incorrect as its using the same transistors in the same direction:

https://external-content.duckduckgo.com/iu/?u=https%3A%2F%2Fi.stack.imgur.com%2F2GSIm.png&f=1&nofb=1

I'm making a guess the resistor placement is doing something I'm not accounting for as it's been a long time since I've had the stuff to mess with my breadboard (most of my electronics prototyping stuff was stolen by a roommate)

The circuits you show are what are known as RTL -- Resistor Transistor Logic. They rely one the circuitry actively pulling the output in one direction, but passively pulling it the other. Furthermore, the input characteristic are very different depending on if you are driving the input HI or driving it LO. This results in highly asymmetric input and output characteristics of each gate; furthermore, the characteristics are depending on the specific type of gate -- a NAND gate has very different characteristics that a NOR gate, for instance. This results in many issues that prevent it from being scalable to large circuits.

The most common form of digital circuitry today is CMOS -- Complementary Metal Oxide Semiconductor. This approach uses complementary pull-up and pull-down structures to create symmetric input and output characteristics that actively assert either a HI or a LO output and that are largely independent of the specific type of gate. This makes designing large digital circuits very scalable.

The common basic CMOS logic structures are shown in this article:

https://learn.digilentinc.com/Documents/313

Look particularly at Figure 4. Notice that in each circuit, each input is driving one PFET gate and one NFET gate. If all of the circuits use the same size NFETs and PFETs, then the input characteristics of every gate type will be identical. For many logic libraries this is done, in part for this reason. But for more critical situations it becomes important get the output characteristics to be the same across different gate types and that requires playing with the transistor gate sizes, which will make the input characteristics logic gate-dependent. But that can be handled by adding dummy gates to equalize the total capacitance seen by any input to be a constant.

Another advantage of CMOS is the extremely huge fanout that is possible. If speed isn't an issue, you can literally use a single CMOS logic gate output to drive millions of other logic gate inputs (I've done it on numerous chip designs).