Re: Simplest possible ALU implementation using only previously-defined chips?

Posted by WBahn on
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/Simplest-possible-ALU-implementation-using-only-previously-defined-chips-tp4034757p4035098.html

Consider two cases: You have the CPU as you have currently designed it (call it CPU_A) and you have another version (CPU_B) in which your decode logic is poorly design and uses an additional ten logic parts. Which CPU is "simpler", the A version of the B version?

Now, you take the B version and package up all of the decode logic into a single part and then instantiate that one decode part in a new design called CPU_C instead of the all of the individual logic parts. Which is simpler now, CPU_A or CPU_C?

Based on your metric, you would have to say that CPU_C is simpler than CPU_A, which is in turn simpler than CPU_B.

However, if I were to manufacturer all three, CPU_B and CPU_C would be indistinguishable.

As an aside, there's no need to flatten the hierarchy to get the improvement in other metrics -- they are by no means mutually exclusive.

Be that as it may, what you are saying about how we partition the design to control the hierarchy has some merit. While it is reasonable to say that having fewer parts TENDS to make the logic at that level of abstraction clearer, this is not always the case and it's a dangerous trap to get too wedded to that notion. What is far more valuable is to have the parts at a given level of abstraction match a partitioning of the project into smaller portions that form a coherent picture at that level of abstraction. Sometimes combining two things can make it harder to understand how things work because the interaction is valuable at the current level of abstraction.

Consider the top level computer. There are two memories, a ROM and a RAM. We could very easily combined these into a single part named MEMORY connected to a part named CPU with six lines going back and forth between them (plus a separate reset signal going into the CPU). But does this really aid in an understanding of the design at this top level of abstraction? Or is a better understanding of the design, at this level, to be had by seeing one part that handles the flow and interaction of the CPU with the instructions and a separate part that handles the flow and interaction of the CPU with the data?