RAM64 address allocation problem within DMux and Mux

Posted by ajksdf on
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/RAM64-address-allocation-problem-within-DMux-and-Mux-tp4035442.html

When I come across the exercise of RAM64, I am thinking of these 3 problems but I still don't know what the correct answers. Any thoughts are welcome. Thank you very much.

1. Why do DMux and Mux need to use the same bit of address while those 8 RAM8 can use the remaining bit?
2. I rmb when doing an exercise in project 1/2, when DMux and Mux were used in the same time.  Their address bit in sel cannot be the same. Why is there a difference?
3. From my observation, those bit of address used only for determining specific register, any other usage for the address?