Re: RAM64 address allocation problem within DMux and Mux

Posted by WBahn on
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/RAM64-address-allocation-problem-within-DMux-and-Mux-tp4035442p4035443.html

It's hard to follow exactly what you are asking.

If you give me a RAM8, then I need three bits to address one of the registers in that block.

If you give me eight RAM8 blocks and I feed the same three address bits to each of them, then all eight are accessing one of their registers and I have eight input lines, eight output lines, and eight load signals.

I can tie all of the inputs together so that a single input goes to all eight.

But I can't tie all of the outputs together, I need a way of using a DIFFERENT set of three address bits to choose one of the eight possibilities. How can that be done?

Similarly, I can't tie all of the load signals together because I want to route the load signal to just one of them. How can that be done?

Does that make sense?