Re: RAM64 address allocation problem within DMux and Mux
Posted by ajksdf on
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/RAM64-address-allocation-problem-within-DMux-and-Mux-tp4035442p4035494.html
In the diagram I draw, for the demultiplexer and the multiplexer. The same bits of address need to be passed in. However, the remaining bits of address need to be be passed to EACH RAM8 as well.
What I would like to ask is that are those address bits are being passed to the suitable place at the same time?
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/RAM64-address-allocation-problem-within-DMux-and-Mux-tp4035442p4035494.html
In the diagram I draw, for the demultiplexer and the multiplexer. The same bits of address need to be passed in. However, the remaining bits of address need to be be passed to EACH RAM8 as well.
What I would like to ask is that are those address bits are being passed to the suitable place at the same time?
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