Re: RAM64 address allocation problem within DMux and Mux

Posted by WBahn on Jan 19, 2021; 4:00am
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/RAM64-address-allocation-problem-within-DMux-and-Mux-tp4035442p4035495.html

I'm pretty sure I know what you mean, but you need to work on making your diagrams so that they convey the information you want. I don't know what any of these signals are because none of them are labeled. What if I assume that you are using the load line in one place but instead you happen to be using the data lines? All kinds of opportunities for miscommunication.

As for timing, the only parts that have clock signals are individual DFF parts. Unless you are registering some of these signals, they all resolve themselves in the same clock cycle. But that's what we want because when I apply the address, data, and a load signal to a memory block, that is the data that I want written to that address on the next rising edge of the clock. Similarly, if I apply an address line to get data from the chip, that is the address whose data I want to be on the memory block's output on the next rising clock edge.