Usefulness of internal pins which are (implicitly) buses?

Posted by neophyte on
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/Usefulness-of-internal-pins-which-are-implicitly-buses-tp4035549.html

I have carefully read A.5.3 on Buses, where internal pins with widths greater than one are treated.  It is clearly written; however, I am perplexed as to the *usefulness* of such internal pins implicitly defined with a width greater than one.

The "Example" given in the text, involving a hypothetical CHIP Foo and its invocation as a part of another (hypothetical) chip, is unhelpful in this regard.  Specifically, one wants to see one or two actual examples of code for simple *complete* chips employing the techniques of (a) implicit definition of internal buses and (b) using these internal buses to simplify coding of parts.

I presume that these internal buses are--somehow--supposed to make coding of chips with multi-bit inputs and outputs (and which themselves use multi-bit parts) easier but for the life of me I can't determine how.  I've been unable to cook up my own real-world examples.

For instance, consider the following attempt to code a simple multi-bit chip that flips the outputs of And16:

CHIP FlipAnd16 {
    IN a[16], b[16];
    OUT out[16];

    PARTS:
    // Put your code here:
And16(a[0..16])=a[0..16]), b[0..16]=b[0..16], out[0..16]=vv;
Not16(in[0..16])=vv, out[0..16]=out[0..16]);

}

When I load the chip into The Hardware Simulator, I receive notification of a syntax error.

So can someone kindly (a) explain the problem with this simple chip; (b) if necessary, provide an alternative simple illustration(s) of the relevant techniques; and (c) generally clarify the *usefulness* of internal buses in coding of multi-bit chips (which invoke multi-bit parts).  Thanks.