Re: Usefulness of internal pins which are (implicitly) buses?

Posted by WBahn on
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/Usefulness-of-internal-pins-which-are-implicitly-buses-tp4035549p4035576.html

neophyte wrote

But, I now take it, internal buses do not obviate the necessity of separate input statements for each bit of an n-ary external input bus, or the necessity of a separate output statement for each bit of an n-ary external output bus.  I gather this is the mistake I made in my chip FlipAnd16.

Let's take a look at your original code.

For instance, consider the following attempt to code a simple multi-bit chip that flips the outputs of And16:

CHIP FlipAnd16 {
    IN a[16], b[16];
    OUT out[16];

    PARTS:
    // Put your code here:
And16(a[0..16])=a[0..16]), b[0..16]=b[0..16], out[0..16]=vv;
Not16(in[0..16])=vv, out[0..16]=out[0..16]);

}

And16(a[0..16])

Do you see where your closing paren is. There's where you biggest syntax error is.

On the line for the Not16, you have two right parens but only one left paren. Another syntax error.

These have nothing to do with busses.

Another issue is that you can't do bus notation on internal signals. That is a limitation of this HDL that most "real" HDLs don't have.

If sounds like your FlipAnd16 is really a Nand16, in which case you could implement it like:

    PARTS:
    // Put your code here:
    And16(a=a, b=b, out=and);
    Not16(in=and, out=out);