ALU Implementation

Posted by Idrisadeniyi on Jul 24, 2021; 12:50pm
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/ALU-Implementation-tp4036186.html

I'm trying to implement ALU chip. Currently, I have an incompletely clear understanding of what to do and I have so far written some truth table, draw out some combination of logic gates, and simulate it on paper to see that the result conforms with what I expect. I have also written the hdl code based on this but, when i ran it, it failed at line 1. I know my solution is flawed but this is my best attempt. please help put me on the right track. Thanks

Below is my HDL.

 Not16(in[0]=zx, out=notzx);
   And16(a=x, b=notzx, out=xandnotzxout1);
   And16(a=notzx, b=x, out=xandnotzxout2);
   Mux16(a=xandnotzxout1, b=xandnotzxout2, sel=zx, out=zxout);
 
   //nx logic
   Not16(in[0]=nx, out=notnx);
   Not16(in=zxout, out=notx);
   And16(a=zxout, b=notnx, out=xandnotnxout);
   Or16(a=notx, b=notnx, out=notxornotnxout);
   Mux16(a=xandnotnxout, b=notxornotnxout, out=nXOut);
      //zy logic
   Not16(in[0]=zy, out=notzy);
   And16(a=y, b=notzy, out=yandnotzyout1);
   And16(a=notzy, b=y, out=yandnotzyout2);
   Mux16(a=yandnotzyout1, b=yandnotzyout2, sel=zy, out=zyout);
      //ny logic
   Not16(in[0]=ny, out=notny);
   Not16(in=zyout, out=noty);
   And16(a=zyout, b=notny, out=yandnotnyout);
   Or16(a=noty, b=notny, out=notyornotnyout);
   Mux16(a=yandnotnyout, b=notyornotnyout, sel=ny, out=nYOut);
   //F logic
   Add16(a=nXOut, b=nYOut, out=xPlusYOut);
   And16(a=nXOut, b=nYOut, out=xAndYOut);
   Mux16(a=xPlusYOut, b=xAndYOut, sel=f, out=xPlusYOrXAndYOut);
   //no Logic
   Not16(in[0]=no, out=notNo);
   Not16(in=xPlusYOrXAndYOut, out=notXPlusYOrXAndYOut);
   And16(a=xPlusYOrXAndYOut, b=notNo, out=noOut1);
   Or16(a=notXPlusYOrXAndYOut, b=notNo, out=noOut2);
   Mux16(a=noOut1, b=noOut2, sel=no, out=noOut, out=out);
   //Zr Logic
   Not(in=true, out=zr);
   Not(in=true, out=ng);