Re: ALU Implementation

Posted by Idrisadeniyi on Jul 26, 2021; 2:40pm
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/ALU-Implementation-tp4036186p4036193.html

Thanks for the clarification. It indeed shed some light on my confusion.

However, as I'm trying to build the ALU chip based on that explanation, I realized I'm not utilizing some input pins which make me become skeptical about my implementation. The following is my hdl:

Mux16(a=x, b=y, sel=zx, out=zxOut); //zx and zy logic
        Not16(in=zxOut, out=notZx); // !x and !y logic
        Inc16(in=notZx, out=xPlusYOut); //2's complement addition
        And16(a=zxOut, b=notZx, out=xAndYOut); // x & y logic
        Mux16(a=xPlusYOut, b=xAndYOut, out=fOut); // f logic
        Mux16(a=zxOut, b=notZx, sel=no, out=noOut, out=out); //no logic
        DMux (in[0]=noOut[0], sel[0]=noOut[0], a=zr, b=ng); // zr and ng logic
         

Another confusion is being able to implement the zr and ng based on out. I'm using DMux to implement that portion. Since out is now a 16bits pin, while zr and ng are 1bit out pin respectively, connecting these pins has been a major challenge.

Thank you for always being there