Re: RISC/CISC Hack Architecture

Posted by rleininger on
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/RISC-CISC-Hack-Architecture-tp4034432p4036651.html

In their book, Computer Architecture:  A Quantitative Approach,  Appendix C.1 Introduction,  authors John L. Hennessy and David A. Patterson characterize the key properties of a RISC architecture as follows:

1. All operations on data apply to data in registers and typically change the
entire register (32 or 64 bits per register).

2. The only operations that affect memory are load and store operations that
move data from memory to a register or to memory from a register, respectively.
Load and store operations that load or store less than a full register
(e.g., a byte, 16 bits, or 32 bits) are often available.

3. The instruction formats are few in number, with all instructions typically
being one size.  (Highlighting is mine.)

Hennessy and Patterson played a substantial role in the development of the RISC architecture, so their pronouncements on the subject should be taken as authoritative.  This small set of restrictions allow for substantial hardware optimization techniques, such as instruction execution pipelining, that can improve the overall instruction execution rates (instructions per second) versus CISC architectures.  Because of this the execution of a program expressed in a RISC instruction set can often outperform the same program written in a CISC instruction set.

Notice that this says nothing about the number of instructions contained in the instructions set.  The adjective "reduced" refers to the fact that the instructions should all be the same size: say 4 byes.  CISC ISA typically have instruction sets of varying length.  While the number of instructions in many RISC ISAs is small, there are some (PowerPC, for example) that have a large number of instructions.

Based on these criteria, the Hack ISA fails to qualify as pure RISC, since requirements 1 and 2 are clearly violated.  The third requirement is satisfied (in the extreme), however.

I would agree with your assessment that the Hack ISA is more CISC than RISC, but for different reasons.  I also agree with WBahn that there is a "spectrum" of ISA architectures in which RISC and CISC (whatever that is), are somewhat widely separated.  The Hack ISA is somewhere between RISC and CISC.

Presently, RISC seems to be winning the "holy war" of best architecture, in terms of devices implemented in actual computing systems.  I think virtually every cell phone these days uses a RISC processor.  Also, most embedded CPUs in commodity products tend to be RISC.