Re: RISC/CISC Hack Architecture

Posted by rleininger on
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/RISC-CISC-Hack-Architecture-tp4034432p4036654.html

When you referred to "C commands", I assumed you were referring to statements written in the C programming language.  The implementation of the C language on a particular computing system has nothing necessarily to do with whether that system's CPU is RISC or CISC.  Computers having CPUs using both RISC and CISC ISAs have successfully hosted C compilers.  I have a C compiler available on my Dell laptop that has an Intel i7 CISC CPU, and I also have a C compiler on my Raspberry Pi Model 4 which has a Broadcom BCM2711 system on a chip with an ARM Cortex-A72 RISC processor.

So, to answer your question:  Yes, this is essentially different from requirements 1 and 2.

Not every CPU ISA satisfies requirements 1 & 2 (for example, the ARM does, the i7 does not), but CPUs of both the RISC and CISC paradigm are capable of running C compilers which "can load, compute, store and branch..."; that is, both RISC and CISC-based computers have instructions "load, compute, store and branch".  The way the instructions work to do these things in hardware is, of course, quite different for RISC versus CISC devices.