Re: RISC/CISC Hack Architecture

Posted by rleininger on
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/RISC-CISC-Hack-Architecture-tp4034432p4036656.html

Ahh, C-instructions, I see.  Sorry I missed that.  I apologize.

So, you are kind of right about the way memory is used in RISC versus CISC ISAs.  All ISAs, both RISC and CISC, have instructions that load and store data into the CPUs internal registers.  All ISAs have instructions that cause the ALU to perform computations to produce a result.  All ISAs have instructions to perform some kind of branching operations.  A key difference between RISC and CISC has to do with "in multiple destinations".  

Requirement 1, I believe, indicates that the operands required for any computation performed by the ALU be located in CPU registers.  Furthermore, the result of a computation always appears in a register.  By register, I mean a storage unit built into the CPU and not a storage unit in main memory (RAM).  In the Hack architecture, the D-register is such a register memory unit.

Requirement 2 says that the only way to read or alter main memory is by specific "load" and "store" instructions that only move program data between a register and a RAM location.

Taken together then, these two requirements mean a single RISC ISA instruction may not use a main memory location directly as an ALU operand or directly as the target storage location of a computation result.  The Hack computer allows these kinds of operations, so it's not RISC.  You may use a RAM location directly as the source of a ALU operand and save the result of a ALU computation directly in RAM.  These are the violations to which I was referring.  It really has nothing to do, at least directly. with performing both of these operations "at the same time", although the "in multiple destinations" seems absolutely correct.

The Hack computer seems to have the interesting capability of being able to perform a computation and store the result in RAM in a single clock cycle ("at the same time"?).  I'm skeptical that any real computer can actually do this.

As I mentioned before, one of the drivers for the RISC architecture was to support the implementation of instruction execution pipelining to improve instruction execution rate in real-world CPUs.  There may be other ways to do this, but the RISC idea seems quite effective in achieving this end.

Since all Hack computer instructions execute completely in a single clock cycle (unlike real-world computers), the need for instruction pipelining unnecessary.  Designing the Hack computer as a RISC machine would seem to hinder its overall speed to execute a program.  I think WBahn had alluded to this in an earlier post of this thread.  I also very much like his idea of thinking of RAM as one big register file.  Again, because all instructions execute in a single clock cycle, this makes excellent sense.  I think it also clearly illustrates his idea of a CISC-RISC "spectrum".

I never know at what technical level to frame responses to a specific question here because I don't know the level of the person posing the question.  If the level of this response is below where you are, I apologize also for this.  I always try to include detail to the best of my ability because I think others reading the thread, who are perhaps at a lower level, may benefit.  Certainly, there are people posting on this site whose level is way above mine, and I am grateful when they correct my misunderstanding of an issue.