Re: Setting A in C-instruction

Posted by WBahn on
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/Setting-A-in-C-instruction-tp4036936p4036940.html

Sounds correct.

One thing to keep in mind is that "tick" and "tock" are merely artifacts of how the hardware simulator is implemented. The fine details of how an actual CPU behaves depends on the exact details of how the DFF is implemented. The author's description implies that it is negative-edge triggered, or possibly uses a master-slave arrangement in which the input is active-HI sensitive by the output is captured on the falling edge.

Both of these are at odds with the symbols they use for their parts, which indicates a positive-edge triggered device. This is possibly due to the authors being CS and not EE folks. It's also possible that this is simply a degree of detail that they treat pretty loosely because it's not germane to the course.

In practice, when using the commonly-used positive-edge triggered registers, at the rising edge the values at the input of each DFF is locked into the register and they then propagate through the combinatorial logic over the course of the rest of the clock cycle. The falling edge does nothing (at least, nothing external to the DFF implementation).

Looking at it in more detail, what is really happening is that the value at the input of each DFF must be stable for some amount of time before the rising clock edge (known as the setup time) and must remain stable for some amount of time after the rising clock edge (known as the hold time). This will be the case as long as the DFF holds the old value at it's output long enough after the rising edge to satisfy the hold time requirement for the DFFs that follow it. This is a function of the propagation delay from input to output of the DFF.

A consequence is that if the DFFs that are used are too fast -- the new value gets to the DFF output too quickly -- you can completely mess up the logic. I actually killed a chip design by switching to a faster DFF without verifying the timing (due to schedule and budget constraints imposed on us by the customer).