Re: Number of NAND gates in the HACK computer

Posted by WBahn on Feb 16, 2025; 1:47am
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/Number-of-NAND-gates-in-the-HACK-computer-tp4038281p4038356.html

One thing to keep in mind about N2T is that it is laser-focused on a simple hierarchical approach that is functional. Efficiency, of any kind, is ruthlessly sacrificed on that alter.

A few examples:

The Xor gate, the design of which is given by the authors, is constructed using a direct implementation of the Boolean expression for the XOR function. That's great for the purposes of the course, where functionality and understandability of that functionality is the goal. But that is probably the worst implementation from an optimization standpoint. In the N2T world, it ends up requiring nine Nand gates and has a total propagation delay equivalent to going through five Nand gates one after another. But the functionality can be implemented using just four Nand gates and suffering only three gate delays, but the mapping between the gate logic and the Xor functionality is anything but obvious. In practice, even the four-Nand solution is seldom used, when speed and space is critical. Instead, it is implemented directly in CMOS using twelve transistors (the same number as in three Nand gates) and having just two gate delays.

Another example is the Add16 chip. The design the authors lead you toward is known as a ripple-carry adder. It is simple, both to comprehend and construct, and it functions properly. It is also abysmally slow due to the carry logic having to trickle through every bit in the circuit. In practice, various designs such as fast-carry and carry-lookahead are used to speed things up, but the concepts behind these approaches are not the easiest to grasp.

So, while it's interesting to count up the number of gates in the Hack, keep in mind that it is not a good reflection of the actual number of transistors that would be used in a real implementation.