Re: Understanding Clock Cycles

Posted by Todun on Apr 13, 2010; 8:39pm
URL: http://nand2tetris-questions-and-answers-forum.52.s1.nabble.com/Understanding-Clock-Cycles-tp712205p717100.html

"... output pins stabilize to new values only at tocks...", from appendix a, suggests that the data-flip-flop(DFF) used is a latch. This means that the DFF is level-tiggered and thus the output reflects the inputs(controlled by the load signal in the case of a register) at the high level(tock) but stores during the low level(tick). By design therefore, the DFF retains data at a time that is one period ago, T-1, and makes it available at the current time T. So starting from time T(start of next tick and end of previous tock), out(T)=[ load(T-1) AND in(T-1) ]. At time +T (tick), out(+T)=out(T)=[ load(T-1) AND in(T-1) ]. During T+1(tock), out(T+1)=[ load(+T) AND in(+T) ]. Then at end of tock(+T+1), out(+T+1)=out(T+1)=out(current-time)=[ load(previous-time) AND in(previous-time) ].

Hopefully all this is correct and helpful. Petzold's Code gives an authoritative, but clear, insight to DFFs.
Todun.