I'm trying to implement ALU chip. Currently, I have an incompletely clear understanding of what to do and I have so far written some truth table, draw out some combination of logic gates, and simulate it on paper to see that the result conforms with what I expect. I have also written the hdl code based on this but, when i ran it, it failed at line 1. I know my solution is flawed but this is my best attempt. please help put me on the right track. Thanks
But there are inputs that modifies the bits before it gets to f. And another element of confusion is that x and y are 16bits and I'm to test each against 1bit value(zx, nx, zy, ny). It's really not clear how to get that implemented.
What f does has nothing to do with how the input and output signals are modified by the other control bits.
The zx anf nx bits make some changes to the 16-bit x-input resulting in a 16-bit signal, call it Fred, and that signal is sent to the adder and the ander. The f input controls which of the two 16-bit outputs of those two is used for further processing.
Remember that you have a part that is specifically designed to let a 1-bit control signal choose which of two 16-bit signals to pass to its output.
As per getting this idea into the hdl, the way I could best think about this process is to break the entire operations into different chunks and setup a truth table for each. for example:
x zx |out
0 0 0
0 1 0
1 0 1
1 1 0
For this combination of bits, I setup logic gates to achieve the outputs; and this is the same approach I've used to implement the rest of the operations of the ALU. If my approach is not correct, please lead me in the right direction. I do understand what the ALU is doing, but to implement it is actually the problem here.
There are many ways to implement the logic and any logic that works is valid.
The authors are definitely trying to steer you toward a particular solution (or at least very close to one) both by the parts they have you build, the way they word the specification, and how they describe it in the text.
Forget about the ALU spec and let's focus on just a tiny piece of the puzzle.
You have two 16-bit signals, let's call them A and B.
You have a 1-bit control signal, called C.
Can you use one (just one) of the parts you have already built so that the output is A if the control signal is a 0 and it is B is the control signal is a 1?
What if the signal B is always 0 (i.e., all sixteen bits are always a 0)?
Now compare how this works to what the zx and zy control signals are supposed to do.
Now let's take another example in which you have a single 16-bit input. Can you think of a way to use one (just one) of the parts you have already built to generate a second signal that is always the bitwise opposite of the first signal?
Can you use another part (just one more) that you have already built to use a 1-bit control signal, called D, so that it outputs the original signal if D is a 0 and the bitwise-negated version of the original signal if D is a 1.
Now compare how this works to what the nx, ny, and no control signals are supposed to do.
You have a data path through the ALU (and later the CPU) that is sixteen bits wide. That data path is like a set of water pipe that flow through a bunch of valves. Those valves, based on the control signals, pick which pipes are allowed to send their data to the next part of the machine.
Thanks for the clarification. It indeed shed some light on my confusion.
However, as I'm trying to build the ALU chip based on that explanation, I realized I'm not utilizing some input pins which make me become skeptical about my implementation. The following is my hdl:
Mux16(a=x, b=y, sel=zx, out=zxOut); //zx and zy logic
Not16(in=zxOut, out=notZx); // !x and !y logic
Inc16(in=notZx, out=xPlusYOut); //2's complement addition
And16(a=zxOut, b=notZx, out=xAndYOut); // x & y logic
Mux16(a=xPlusYOut, b=xAndYOut, out=fOut); // f logic
Mux16(a=zxOut, b=notZx, sel=no, out=noOut, out=out); //no logic
DMux (in=noOut, sel=noOut, a=zr, b=ng); // zr and ng logic
Another confusion is being able to implement the zr and ng based on out. I'm using DMux to implement that portion. Since out is now a 16bits pin, while zr and ng are 1bit out pin respectively, connecting these pins has been a major challenge.
Describe, in words, how YOU would look at a 16-bit value and determine True or False to the question of whether that 16-bit value was positive or negative. Or how you would determine if it represents the value zero.
Look at the two's complement representation described in the text and look for a feature that ALL strictly negative numbers have that ALL strictly positive numbers do not. Hint, this feature is why zero is considered non-negative by pretty much every programming language on the planet.