ALU Implementation

[WBahn]

So look at those last two lines of the .out file. The only difference between the ALU output is the least significant bit. So walk through your logic and see why that bit in the output is causing the zr bit to get set when it shouldn't.

[WBahn]

Here's a hint. Look very carefully at how many bits wide each of your signals is that generates your zr bit.

[Idrisadeniyi]

I found out that zr is taking its value from out at the specified index out[0]=zr. So it runs fine until out at LSB is set to 0 where zr is meant to be 0, so zr returns 1. I think the distinction you spoke about is coming into play, as it's evident that i cannot possibly get zr by only piping to out at LSB or any other position in the bus.

Can I get more light on this?

[WBahn]

That's right. You need to Or all 16 bits of the SINGLE ALU out value TOGETHER. That's not what the Or16 part does. It takes TWO 16-bit values and Ors corresponding bits with each other producing 16 outputs.

Look at your list of parts and see if you have something that takes many inputs and ORs them together to produce a single output. Then read back through the things I've asked you to do and see how they apply to using that part to Or all sixteen bits of the ALU output together.

[Idrisadeniyi]

Thanks. I have it implemented now. zr and ng appears to be producing the expected results.

But out is strangely failing the test at line 30. My out file is producing:
             x                                 y                 zx  nx  zy ny   f   no                 out            zr  ng
| 0000000000010001 | 0000000000000011 | 1 | 1 | 0 | 1 | 1 | 1 | 0000000001000100 | 0 | 0 |

 Instead of this:
| 0000000000010001 | 0000000000000011 | 1 | 1 | 0 | 1 | 1 | 1 | 0000000000000100 | 0 | 0 |

[WBahn]

That's progress!

Now walk through what the logic SHOULD be doing, based on the specification, and see if you agree with the result in the .cmp file. Compare this with what these control signals say the operation should be from the table of the 18 defined operations you were given. If you don't agree with the .cmp file, then the problem lies with your understanding of the specification and that needs to get fixed first.

Once you agree that the .cmp file is correct, the walk through YOUR design for that set of inputs and see if you agree that it produces what is in the .out file. If it doesn't, then the problem is in understanding the logic you implemented and that needs to get fixed next. Once you understand why it is producing what it produces, see where it deviates from what the spec says it should produce.

[Idrisadeniyi]

I have studied the .cmp and the given table and i understood how it's computing and producing the result.

I went through my hdl several times and the chip parts seems to be wired properly and I could not see why out produces 2 high bits on that row instead of 1.