AND gate. a=1, sel=1, but out = 0? HowIsThisPossible? -- Mux

[zoobra]

Hellooooo Friends!


Why is the "And" outputting 0 when both input values are 1?




And why is the Eval button disabled?

Here is the script in Mux.hdl:

CHIP Mux
{
    IN a, b, sel;
    OUT out;

    PARTS:
    Not (in=sel, out=notSel);
    And (a=a, b=sel, out=aAndSel);
    And (a=b, b=notSel, out=aAndNotSel);
    Or (a=aAndSel, b=aAndNotSel, out=out);
}

[cadet1620]

zoobra wrote

Why is the "And" outputting 0 when both input values are 1?

And why is the Eval button disabled?

Usually when the Eval button is disabled, one or more of the pins in the OUT section are not connected to anything. It may be one of the chips being used in the PARTS section that has this problem.

Most commonly, this problem is caused by using a chip in the PARTS section that you haven't built yet. That chip will not have any implementation, but because it exists it will override the built in chip.

This is also consistent with And(1,1) = 0. If the And chip has no connection to its out pin, the output will always be 0.

You should build your parts in the order they are described in section 1.2 to avoid this problem.

--Mark

[zoobra]

@cadet1620

"End of script - Comparison ended successfully"
 



You were absolutely right!


I hadn't built the other gates



Thanks a lot, @cadet1620.