Building chips problem.

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Re: Building chips problem.

GustavoB
This post was updated on .


I've tried to make the cannonical representation with the example on page 9, then I just searched for a truth table generator and then I gave him this expression:

(¬x Λ y Λ ¬z) V (x Λ ¬y Λ ¬z) V (x Λ y Λ ¬z)

And the truth table matched exactly the truth table on figure 1.1 then I started to mentally mount the circuit for this boolean expression and I guess this circuit would be a big one. Does it's size matter? When I searched for multiplexor circuits, I've found some circuits and also some boolean expressions which are smaller.

For example, the multiplexor has this boolean expression:

[Edited]

But with cannonical representation, I have to make it like this:

(aΛ¬bΛ¬s) V (aΛbΛ¬s) V (¬aΛbΛs) V (aΛbΛs)

Is this difference of size important? And, what do I need to know to build smaller boolean expressions?






My name is Beuys von Telekraft, and I am a scientist. I work in my laboratory night and day.
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Re: Building chips problem.

cadet1620
Administrator
The important thing about the canonical representation is that it always exists and therefore any function that can be described in a truth table can be generated.

The canonical representation is rarely the simplest form of a function. There are various ways to find reduced forms.  One good method is to use Karnaugh Maps. Search the forum for "karnaugh". Also see http://www.facstaff.bucknell.edu/mastascu/elessonshtml/Logic/Logic3.html. Using Karnaugh Maps will reduce the fig. 1.1 function to
    (x . ~z) + (y . ~z)
You can use Boolean algebraic rules to reduce this to
    (x+y) . ~z

For TECS it is not necessary to find optimized implementations; any implementation that passes the tests is OK. For more complex parts the canonical representation is unmanageable -- the canonical representation for the sum output of a 16-bit adder has 32768 terms -- so it is important to learn how to design using abstraction.

--Mark

[Please edit your post to remove the simplified implementation of Mux. We want students to find this on their own.]

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Re: Building chips problem.

ybakos
In reply to this post by GustavoB
Yes, good question GustavoB. What's cool is that to simplify a circuit, we can work on the Boolean function that represents its functionality and refactor it.

It comes down to becoming skilled with the rules of Boolean algebra. We should be familiar with DeMorgan's law (and his storied life) as well as things like this:
http://mines.humanoriented.com/410/books/boolean_algebra.pdf
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Re: Building chips problem.

GustavoB
Thanks for the suggestions.

I'm now freely transforming truth tables to cannonical expressions and I'm on the way of understanding Karnaugh maps, I've also had to read about Grey's code. I have some questions by now:

-I know how to use the Cannonical expressions but on a mechanical way: I know what tool I should use, but I don't "feel" the concept, I mean when I think about summing two numbers I can "feel" the numbers spinning, like 0 goes up to 9, when 9 is reached, it spins again and become 0, spinning the next number on the left to 1 and then repeating this process ad infinitum. In the cannonical representation, I feel nothing, I just know that this tool is available and I know what it does. Should I worry about that?

-Can I keep asking my questions here or is it better to create new posts with new questions?
My name is Beuys von Telekraft, and I am a scientist. I work in my laboratory night and day.
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Re: Building chips problem.

cadet1620
Administrator
Canonical representations are very mechanical; there isn't much there to feel. If the true outputs were holes in a in a dam, you plug each hole and the dam stops leaking. Don't get hung up on becoming a Karnaugh Map expert; they are of limited use beyond chapter 1.

From your description of addition, it sounds like you are a visual learner. You might want to play with LogiSim, http://ozark.hendrix.edu/~burch/logisim. It's a visual digital logic simulator.  You will still need to translate the circuits you build in LogiSim to HDL to use them with TECS.

If your questions are on a different subject, it is better to start a new post.  This will help other people who have the same question find the discussion of their problem.

--Mark
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Re: Building chips problem.

GustavoB
Thank you for the suggestion, I was using this truth table generator:

http://turner.faculty.swau.edu/mathematics/materialslibrary/truth/
My name is Beuys von Telekraft, and I am a scientist. I work in my laboratory night and day.
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Re: Building chips problem.

GustavoB
In reply to this post by cadet1620
Hey, building the logical circuits on logisim is way easier!
My name is Beuys von Telekraft, and I am a scientist. I work in my laboratory night and day.
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Re: Building chips problem.

GustavoB
In reply to this post by cadet1620
Mark, Logisim is SO laggy when handling the 16bit chips, what can I do to improve it's performance? I've looked at the task manager and the java app is using only ~80MBram, can I do something to improve it?
My name is Beuys von Telekraft, and I am a scientist. I work in my laboratory night and day.
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Re: Building chips problem.

cadet1620
Administrator
Yes, when you have lots of nested subcircuits LogiSim slows down a lot. The bet that you can do is to use its built-in parts to do the heavy work. For example if you are trying to use the Bit/Register/RAM8/etc. hierarchy to build bigger RAMs you would be better to use the built-in RAM part.

If you want it to look more like a TECS RAM, you could wrap a 16K built-in RAM in a part called RAM16K.

Let's not pollute the forum with LogiSim discussions. If you want to talk more about it, email me directly. (More|Reply to author.)

--Mark
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