
This is a chip of my own design used to implement the Mux4Way16 chip. If you would prefer the complete code for each chip used in my Mux4Way16 implementation, please let me know. Also let me know where to put them(email, multiple messages, etc.)
Below is the code snippet of the internal pin using a bus logic:
/** s0, s1 are singlebit internal pins. s2[0..15] is the internalpin bus causing
the failure in simulation but looks perfectly fine on paper(circuit diagram).
*/
And3Way( a=a[0], b=s0, c=s1, out=s2[0] );
And3Way( a=a[1], b=s0, c=s1, out=s2[1] );
...
And3Way( a=a[15], b=s0, c=s1, out=s2[15] );
So after running into that wall, I thought about making a buschip that had input==output. The Bus16Way chip works in the Bus16Way simulation but does not work in the context of the Mux4Way16 simulation. Below is a code snippet of the Bus16Waychip used in Mux4Way16:
/** The output of these And3Way gates are the inputs for a single
Bus16Way gate. This is with the hopes that since the circuitinterface
for the Bus16Way specifies the output to be 16bits then it follows that,
according to appendix A, the internal pin made to be its output will have
its specification/connectivity implied.
*/
// 3input And gates with singlebit output
And3Way( a=a[0], b=s0, c=s1, out=s2a );
And3Way( a=a[1], b=s0, c=s1, out=s2b );
And3Way( a=a[2], b=s0, c=s1, out=s2c );
And3Way( a=a[3], b=s0, c=s1, out=s2d );
And3Way( a=a[4], b=s0, c=s1, out=s2e );
And3Way( a=a[5], b=s0, c=s1, out=s2f );
And3Way( a=a[6], b=s0, c=s1, out=s2g );
And3Way( a=a[7], b=s0, c=s1, out=s2h );
And3Way( a=a[8], b=s0, c=s1, out=s2i );
And3Way( a=a[9], b=s0, c=s1, out=s2j );
And3Way( a=a[10], b=s0, c=s1, out=s2k );
And3Way( a=a[11], b=s0, c=s1, out=s2l );
And3Way( a=a[12], b=s0, c=s1, out=s2m );
And3Way( a=a[13], b=s0, c=s1, out=s2n );
And3Way( a=a[14], b=s0, c=s1, out=s2o );
And3Way( a=a[15], b=s0, c=s1, out=s2p );
// this chip takes 16 singlebit inputs and outputs
// a 16bit bus version of the inputs
Bus16Way( a0=s2a ,a1=s2b ,a2=s2c ,a3=s2d ,a4=s2e ,a5=s2f ,a6=s2g ,a7=s2h ,a8=s2i ,a9=s2j
,a10=s2k ,a11=s2l ,a12=s2m ,a13=s2n ,a14=s2o, a15=s2p, out=s2 );
I also tried variations of this, just to make the bus accepted. Like this one below which takes 16 internal pin inputs and outputs 16 internal pin outputs to avoid uses buses completely:
/** Code snippet 3*/
Bus16In16Out( a0=r2a ,a1=r2b ,a2=r2c ,a3=r2d ,a4=r2e ,a5=r2f ,a6=r2g ,a7=r2h ,a8=r2i ,a9=r2j ,a10=r2k ,a11=r2l ,a12=r2m ,a13=r2n ,a14=r2o, a15=r2p, out0=s2a, out1=s2b, out2=s2c, out3=s2d, out4=s2e, out5=s2f, out6=s2g, out7=s2h, out8=s2i,out9=s2j, out10=s2k, out11=s2l, out12=s2m, out13=s2n, out14=s2o, out15=s2p);
And3Way( a=a[0], b=s0, c=s1, out=s2a );
And3Way( a=a[1], b=s0, c=s1, out=s2b );
And3Way( a=a[2], b=s0, c=s1, out=s2c );
And3Way( a=a[3], b=s0, c=s1, out=s2d );
And3Way( a=a[4], b=s0, c=s1, out=s2e );
And3Way( a=a[5], b=s0, c=s1, out=s2f );
And3Way( a=a[6], b=s0, c=s1, out=s2g );
And3Way( a=a[7], b=s0, c=s1, out=s2h );
And3Way( a=a[8], b=s0, c=s1, out=s2i );
And3Way( a=a[9], b=s0, c=s1, out=s2j );
And3Way( a=a[10], b=s0, c=s1, out=s2k );
And3Way( a=a[11], b=s0, c=s1, out=s2l );
And3Way( a=a[12], b=s0, c=s1, out=s2m );
And3Way( a=a[13], b=s0, c=s1, out=s2n );
And3Way( a=a[14], b=s0, c=s1, out=s2o );
And3Way( a=a[15], b=s0, c=s1, out=s2p );
All failed in simulation with differing and incomplete error messages. Now I'm thoroughly confused as to the interplay between internal pins, chips,and the IN/OUT signals.
Thanks,
Todun.
