Busing internal pins

[Todun]

I am trying to create a multi-bit/multi-way multiplexor from scratch using basic gates. However, when I try to make an internal pin(an intermediate signal in my circuit diagram), as an output or input, that is a bus-line(using the index notation to abstract the bus), the Hardware Simulator always fails my hdl. I know the logical wiring is correct(according to my circuit diagram) but I suspect that the Hardware Simulator doesn't allow internal pins to be bus-lines. Am I correct? If correct, is there a solution besides creating extra logic to handle this problem?
Thanks!

[ybakos]

It sounds like you might be running into the rule that 'internal buses can't be sub-bused'.

See this thread.

If this is a chip of your own design (not one of the 'official' chips to be built in the book) please post your HDL. Otherwise just post a little snippet.

[Todun]

This is a chip of my own design used to implement the Mux4Way16 chip. If you would prefer the complete code for each chip used in my Mux4Way16 implementation, please let me know. Also let me know where to put them(email, multiple messages, etc.)
Below is the code snippet of the internal pin using a bus logic:

         /** s0, s1 are single-bit internal pins. s2[0..15] is the internal-pin bus causing
              the failure in simulation but looks perfectly fine on paper(circuit diagram).
         */
         And3Way( a=a[0], b=s0, c=s1, out=s2[0] );
         And3Way( a=a[1], b=s0, c=s1, out=s2[1] );
         ...
         And3Way( a=a[15], b=s0, c=s1, out=s2[15] );

So after running into that wall, I thought about making a bus-chip that had input==output. The Bus16Way chip works in the Bus16Way simulation but does not work in the context of the Mux4Way16 simulation. Below is a code snippet of the Bus16Way-chip used in Mux4Way16:

        /** The output of these And3Way gates are the inputs for a single
              Bus16Way gate. This is with the hopes that since the circuit-interface
              for the Bus16Way specifies the output to be 16-bits then it follows that,
              according to appendix A, the internal pin made to be its output will have
              its specification/connectivity implied.
        */


        // 3-input And gates with single-bit output
        And3Way( a=a[0], b=s0, c=s1, out=s2a );
        And3Way( a=a[1], b=s0, c=s1, out=s2b );
        And3Way( a=a[2], b=s0, c=s1, out=s2c );
        And3Way( a=a[3], b=s0, c=s1, out=s2d );
        And3Way( a=a[4], b=s0, c=s1, out=s2e );
        And3Way( a=a[5], b=s0, c=s1, out=s2f );
        And3Way( a=a[6], b=s0, c=s1, out=s2g );
        And3Way( a=a[7], b=s0, c=s1, out=s2h );
        And3Way( a=a[8], b=s0, c=s1, out=s2i );
        And3Way( a=a[9], b=s0, c=s1, out=s2j );
        And3Way( a=a[10], b=s0, c=s1, out=s2k );
        And3Way( a=a[11], b=s0, c=s1, out=s2l );
        And3Way( a=a[12], b=s0, c=s1, out=s2m );
        And3Way( a=a[13], b=s0, c=s1, out=s2n );
        And3Way( a=a[14], b=s0, c=s1, out=s2o );
        And3Way( a=a[15], b=s0, c=s1, out=s2p );

        // this chip takes 16 single-bit inputs and outputs
        // a 16-bit bus version of the inputs
        Bus16Way( a0=s2a ,a1=s2b ,a2=s2c ,a3=s2d ,a4=s2e ,a5=s2f ,a6=s2g ,a7=s2h ,a8=s2i ,a9=s2j  
          ,a10=s2k ,a11=s2l ,a12=s2m ,a13=s2n ,a14=s2o, a15=s2p, out=s2 );

I also tried variations of this, just to make the bus accepted. Like this one below which takes 16 internal pin inputs and outputs 16 internal pin outputs to avoid uses buses completely:

        /** Code snippet 3*/
        Bus16In16Out( a0=r2a ,a1=r2b ,a2=r2c ,a3=r2d ,a4=r2e ,a5=r2f ,a6=r2g ,a7=r2h ,a8=r2i ,a9=r2j ,a10=r2k ,a11=r2l ,a12=r2m ,a13=r2n ,a14=r2o, a15=r2p, out0=s2a, out1=s2b, out2=s2c, out3=s2d, out4=s2e, out5=s2f, out6=s2g, out7=s2h, out8=s2i,out9=s2j, out10=s2k, out11=s2l, out12=s2m, out13=s2n, out14=s2o, out15=s2p);
               
        And3Way( a=a[0], b=s0, c=s1, out=s2a );
        And3Way( a=a[1], b=s0, c=s1, out=s2b );
        And3Way( a=a[2], b=s0, c=s1, out=s2c );
        And3Way( a=a[3], b=s0, c=s1, out=s2d );
        And3Way( a=a[4], b=s0, c=s1, out=s2e );
        And3Way( a=a[5], b=s0, c=s1, out=s2f );
        And3Way( a=a[6], b=s0, c=s1, out=s2g );
        And3Way( a=a[7], b=s0, c=s1, out=s2h );
        And3Way( a=a[8], b=s0, c=s1, out=s2i );
        And3Way( a=a[9], b=s0, c=s1, out=s2j );
        And3Way( a=a[10], b=s0, c=s1, out=s2k );
        And3Way( a=a[11], b=s0, c=s1, out=s2l );
        And3Way( a=a[12], b=s0, c=s1, out=s2m );
        And3Way( a=a[13], b=s0, c=s1, out=s2n );
        And3Way( a=a[14], b=s0, c=s1, out=s2o );
        And3Way( a=a[15], b=s0, c=s1, out=s2p );

All failed in simulation with differing and incomplete error messages. Now I'm thoroughly confused as to the interplay between internal pins, chips,and the IN/OUT signals.

Thanks,
Todun.

[ybakos]

Email me your whole Mux4Way16.hdl

By the way, what is your motivation for creating this?

[Todun]

Just checking to see if you've gotten the email.

Thanks!
Todun.

[ybakos]

Your error is caused by the incorrect labeling of Not's input pin. The input pin of Not is 'in' not 'a'.

[Todun]

Uhm..But in my Not chip-interface, I specifically made the IN to be a and not in. I sent you an email of the NOT specification. Must I change it to in before it can work?

[ybakos]

No, the input pin labels are driven by your implementation. Mine fails because I don't have your custom chip. I also don't have your custom Or4way or whatever it is, so I can't load your Mux4Way16.

[Todun]

I'm sorry to keep troubling you, I just don't know what is wrong. I have sent you all the composite chips of the Mux4Way16 chip. Please let me know if any is missing.

Thanks!
Todun.

[ybakos]

Your Mux4Way16 attempts to to wire the output of one of your Bus16Way's (a 16-bit bus) into a 1-bit input of your Or4Way. To me, this has nothing to do with the bussing rules, internal pins, etc. You're simply incorrectly trying to stuff 16 bits into 1.

See line 112 of your Mux4Way16.

Good luck.

[Todun]

Thank you very much! Sorry for the wild goose chase. It now works.

Todun.

[Stephen Davies]

I'd love to see the thread on "internal buses can't be sub-bused," but the link in your post is broken. Can you direct me?

[cadet1620]

Stephen Davies wrote

I'd love to see the thread on "internal buses can't be sub-bused," but the link in your post is broken. Can you direct me?

The target's probably been deleted.

The error message reflects a limitation in HDL.  What you need to do is to create two different internal buses that are the widths you need.  For example, if you need the 16-bit word in one place and the low byte in another you can write
    And16(a=foo, b=bar, out=and_word, out[0..7]=and_low_byte);

--Mark

[cadet1620]

I found the current head of the internal buses can't be sub-bused thread.

--Mark