CPU, Don't Know where to start

[Tom Wiggins]

I am having trouble designing the decoder, I don't even know what the decoder does, i mean I know it decodes the instructions but I can't wrap my head around it . I also have trouble understanding the ALU implementation, when I made the ALU, it had zx, nx , ny ect , I don't see any of that in figure 5.9

[ybakos]

The "decoder" can be misleading due to the way it is represented in the diagram. Do not think of it as a single chip. It really represents "a bunch of stuff you need to implement to get the CPU to work."

Regarding the ALU, here's a tip. Look at the series of bits for a particular operation (figure 2.6). Then look at the series of bits for a C-instruction (figure 4.3). See anything similar? Hmmm...

[cadet1620]

The thing to understand in Figure 5.9 is that the "C" signals are a lot of individual signals. If you could magnify the figure you'd see the "C"s going into the top of the ALU as

    

Magnifying the "C" outputs from the Decode block you'd see

    

As Ybakos said, Decode is just a bunch of logic in the CPU. Here's a hint to get you started:

Some of the control signals must only be asserted (true) during A-instructions and some of them only during C-instructions. You will need a signal that indicates when an A-instruction is executing. It will also be handy to have a signal that indicates a C-instruction.  You can generate these as

    // Instruction decoder
    Not(in=instruction[15], out=aInst);
    Not(in=aInst, out=cInst);

When do you want to load the A register?  For all A-instructions and for C-instructions with the d1 bit set. So you need a control signal to hook to the A-register's load:
    loadAreg = aInst | (cInst & d1)

If you need more help, feel free to email me directly.

--Mark

[Tom Wiggins]

Thanks, I'll see what I can do

[akazabobo]

i am trying to design the cpu chip.
im starting  to understand the logic of your blessed hint but it seems to me you are assuming the instruction is an a instruction with this code:
" // Instruction decoder
    Not(in=instruction[15], out=aInst);
    Not(in=aInst, out=cInst); "

if its a c instruction then aInst=0,  cInst=1 and then when you
loadAreg = aInst | (cInst & d1)
 d1  will be the d1 of an a instruction..

am i wrong? what am i missing out?

thank you

[ybakos]

akazabobo, Consider the Hack assembly language for a moment. There are two specific instructions that would cause a value to be written to the A register:

- an A instruction, eg, @123
- a C instruction, where A is the dest, eg: A=D

So think about this: you're the A register. When should your load input be on? When the 16-bit instructions represent an A instruction; or a C instruction and the A is the dest.

[cadet1620]

akazabobo wrote

i am trying to design the cpu chip.
im starting  to understand the logic of your blessed hint but it seems to me you are assuming the instruction is an a instruction with this code:
" // Instruction decoder
    Not(in=instruction[15], out=aInst);
    Not(in=aInst, out=cInst); "

if its a c instruction then aInst=0,  cInst=1 and then when you
loadAreg = aInst | (cInst & d1)
 d1  will be the d1 of an a instruction..

am i wrong? what am i missing out?

thank you

'd1' is instruction[5], regardless of the type of instruction. The issue is that instruction bits defined for c-instructions should not cause actions that are not related to c-instuctions. The above line of HDL can be read "load the A register if this is an a-instruction, or if this is a c-instruction with d1 set."

Note that in the special case of 'd1' there is a logical reduction that will allow you to forego the "cInst &", but is would be bad form. The problem is that if in the future you were to add another type of instruction to your CPU the reduction may no longer be valid and would cause a bug that might be hard to find.

--Mark

[Nick Lee]

I'm really struggling to understand how this allows the CPU to distinguish between an A-instruction or C-instruction:
    // Instruction decoder
    Not(in=instruction[15], out=aInst);
    Not(in=aInst, out=cInst);

Because doesn't it only work if the current incoming instruction has an opcode of 1 (i.e. is a C instruction)?

If an incoming instruction has an opcode of 0 (i.e. an A instruction) then won't the output of the first Not gate (aInst) be 1? How can it be called aInst if it's opcode is 1? I really think I am missing something here.

The only way I can think to decode an instruction would be to use a DMux16 chip using instruction[15] as the sel bit, but unfortunately that is not a part of the Hack chipset so I am currently stuck.

Would really appreciate some shedding of light here.

[cadet1620]

Nick Lee wrote

I'm really struggling to understand how this allows the CPU to distinguish between an A-instruction or C-instruction:
    // Instruction decoder
    Not(in=instruction[15], out=aInst);
    Not(in=aInst, out=cInst);

Because doesn't it only work if the current incoming instruction has an opcode of 1 (i.e. is a C instruction)?

If an incoming instruction has an opcode of 0 (i.e. an A instruction) then won't the output of the first Not gate (aInst) be 1? How can it be called aInst if it's opcode is 1? I really think I am missing something here.

'aInst' is a control signal that is true only when executing a-instructions.
'cInst' is a control signal that is true only when executing c-instructions.

These two signals are used to control data paths and operations during instruction operation.
For instance, when does the A register need to be loaded? It needs to be loaded for all a-instructions and for any c-instruction that has the d1 bit (instruction[5]) set.

And (a=cInst, b=instruction[5], out=destA);
Or (a=destA, b=aInst, out=loadAreg);
...
ARegister (..., load=loadAreg, ...);

--Mark

[Nick Lee]

Thanks for the fast response Mark! I will try to figure this out. I don't know if it's just me over complicating things but it seems like out of all the chips we've implemented up to this point in the course, CPU.hdl is by far the hardest to implement and wrap my head around.

If you know of any video tutorial on Project 5 please do let me know. Kind of like this one (password: CRCP) posted by ybakos. I tried searching youtube and stuff and couldn't find anything that went in depth.

[cadet1620]

The Coursera Nand2Tetris part 1 course has videos for everything, but I think that you can't access the chapter 5 videos until you've done the first 4 chapters. (All you should need to do is submit your working solutions to chapters 1-4.)

One approach to implementing the CPU is to print a copy of figure 5.9 from chapter 5 and write appropriate names for all the control signals. For example, the control signal going into the D register is "loadDreg". (Note that the ALU control signals are multiple individual signals.)

Also, write in names for all the wires/buses between the parts.

Next, write all the HDL for the parts shown in figure 5.9 using your control signal names. For instance, the D register will be something like

DRegister (in=aluOut, load=loadDreg, out=dRegOut);

Then you need to think about what combination of instruction bits generate each of the control signals. For instance, loadDreg should be true when a c-instruction has d2 (bit 4) set.

--Mark

[Nick Lee]

Ok thanks for that, I'll take up your suggestion and try it that way