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I set the load-bit of the DRegister to "instruction[4]", without checking whether I am
dealing with an A- or an C-instruction beforehand, and it still passed CPU.tst. It failed
at least one of the Computer.tst's, I do not remember which one, so the error was caught
by a test after all. I do not have the faulty version of my CPU.hdl anymore, can someone
reproduce this behavior? If so, maybe a section could be added to CPU.tst where an
A-instruction with instruction[4] (and maybe [3] and [5]) set is fed to the CPU and
immediately after that it checks that the contents of the Dregister did not change?
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