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I was just curious if there is a way to get the hardware simulator to report on the time taken to execute a logic design. The reason I ask is because when you spoke of the inefficiency of a ripple-carry adder, I went and looked up an FPGA website to see how the Carry Look Ahead Adder works, and managed to implement it, but it's impossible to pick the difference in efficiency, without seeing some kind of internal clock of the hardware simulator. Would it be possible for you to add this functionality, or is there some other way to achieve it?
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