Chapter 1 And gate wierd issue

classic Classic list List threaded Threaded
3 messages Options
Reply | Threaded
Open this post in threaded view
|

Chapter 1 And gate wierd issue

fuzzylr
Greetings,  I am having an odd issue that I can't seem to get around.  I know my Not gate is configured properly.  The tests run clean and I am not getting any errors.  However, when I add the not into the Nand for the And gate the Not is processing the input values properly.

Here is what I am seeing when I debug.  When I watch the values during the testing for the And gate the Not gate is defaulting and staying with 1 the whole time.  So the output value is 0.  When it reaches the set a =1, b = 1 it still comes to zero instead of 1.  Might any of you know why it is doing this?  I have tried to avoid posting up and I have searched the forums.  This question was asked once before but died shortly after the question was asked.

Fuzzy
Reply | Threaded
Open this post in threaded view
|

Re: Chapter 1 And gate wierd issue

cadet1620
Administrator
Feel free to email me your And.hdl and I'll give you hints to help you get it working.

--Mark
Reply | Threaded
Open this post in threaded view
|

Re: Chapter 1 And gate wierd issue

fuzzylr
Thank you.  I have sent you the project 01 zipped up.  I was attending a local hackers / makers meeting at the local library.  Pretty neat stuff.