|
|
|
|
With regard to the exercises in Chapter 1, I'm slightly confused about whether the goal is to implement all chips using just nand gates, or whether to compose logic from e.g. and, or, not.
I may be incorrect in my findings but it appears e.g. that I can construct Xor with fewer "raw" nand gates than the number required if i use and, or and not.
Is the goal of the exercises to achieve the most efficient result, or just the easiest implementation?
|
|
Administrator
|
The goal is to achieve a correctly functioning implementation.
There is no consideration for "efficiency", which is an ambiguous concept anyway unless the metric for it is clearly defined -- fewest transistors, fastest speed, etc.
Consider the Not gate. Yes, that can be implemented with a single Nand gate, but a Nand gate (in standard CMOS) requires four transistors, but a Not gate can be directly implemented using just two transistors and be slightly faster.
Even more to the point, how would you implement a 2-input Nor gate? In standard CMOS, it is a done with four transistors and is essentially the same speed as a 2-input Nand gate. But if you have to build it out of Nand gates, you are looking at needing four Nand gates for a total of sixteen transistors and it will be only a third the speed.
So the very notion of constructing a computer with nothing but Nand (and DFF) chips means that the focus is on a seeing a clear structural hierarchy at the expense of anything related to performance. No one in their right might would ever build a real computer this way, but understanding exactly how it could be done has tremendous educational value.
Having said all of that, while there is no need to try to come up with elegant implementations for any of the parts, there is no harm in doing so, either, and the practice in manipulating logic circuits has value.
|
|
|
Ah ok I misunderstood page 27 where it says "the only building blocks that you can use are primitive Nand gates and the composite gates that you will gradually build on top of them".
I interpreted this to mean that the only primitive gate aviailable is the Nand gates and that all other gates were to be considered composites (so Not would only be built out of Nands).
On the same page there is mention of "efficiency considerations such as the number of elementary gates used in constructing a composite gate..." " Such considerations are critically important in practice..."
But, from what you say it sounds like the authors merely wanted any functioning solution, and I note that the example Xor hdl on page 16 uses composite gates rather than raw nand gates.
Out of interest, do you speak on behalf of the authors WBahn or are you just an interested party?
|
|
Administrator
|
No, you weren't misreading it.
For THIS project, all of the combinatorial logic blocks are constructed using nothing but 2-input Nand gates, either directly or indirectly. You also have the sequential logic portion of the design and those are all build using a D-type flip flop as the primitive building block.
For THIS project, there is no real point in trying to design it with "efficiency" in mind, in large part because whatever metric you might have used to determine if one design is more efficient than another design largely loses its meaning when you are constrained to use just 2-input Nand gates as your primitive building block.
So, for THIS project, focus first and foremost on getting ANY design that functions correctly. The degree to which you can come up with an "elegant" design is nice and can be good practice, but completely immaterial as far as completing the project is concerned.
Yes, the authors only care about a functioning solution. That's the only thing that the test files check for. The Xor gate example that they show in Figure 1.6 use is a shining case in point. They use higher-level gates to implement the logic because doing so makes the mapping between the Boolean logic that describes a 2-input Xor gate and the logic design glaringly obvious. This is very much in line with their primary approach of increasing the complexity and level of abstraction of the design one small step at a time and then using each level as the basis for the next level.
But from any reasonable metric for "efficiency" it is an absolutely horrible design. An Xor can be implemented, even under the constraints of this project, using four 2-input Nand gates yielding a design that uses 16 transistors and exhibits 3 gate delays. But their design would use 36 transistors and exhibit 5 gate delays. But that doesn't matter for THIS project, because the ONLY thing that matters is that the design function correctly.
No, I don't speak on behalf of the authors, but I have had quite a bit of interaction with them and I've gotten a pretty good understanding of what their goals and rationale are for how they are going about things the way they do (which doesn't mean that I can guarantee that I'm right about that in any particular instance).
|
|
Locked
