1) read the appendix A1-A6 on HDL
2) you can't use standard language syntax for it.
CHIP And { // 'And' is the name of the chip
IN a, b; // the digital inputs have values of 0,1
OUT out; // the digital out has values of 0,1
PARTS:
// Implementation missing.
// Implement the chips in the order recommended on the project 1 web page
// a hint: you have to use Nand(...) and Not(...) to implement the And, so its best to start off with the Not
// gate aka. inverter
MarZ