Condition to logic

[nandona]

Im currently trying to do mux and I have a really hard time going from out = a if sel == 0 else b

Like I cant figure out how to determine whats the value of sel

[ivant]

Let's start with a simpler problem: create a circuit which has 2 inputs: in and sel and one output out. The output should be equal to in if sel == 1 and to 0 otherwise.

What would be the truth table for this circuit?

[nandona]

in  |  sel |  out

0  |  0  |  0

1  |  0  |  0

0  |  1  |  0

1  |  1  |  1

On Fri, Apr 3, 2020 at 11:03 PM ivant [via Nand2Tetris Questions and Answers Forum] <[hidden email]> wrote:

Let's start with a simpler problem: create a circuit which has 2 inputs: in and sel and one output out. The output should be equal to in if sel == 1 and to 0 otherwise.

What would be the truth table for this circuit?

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[ivant]

Ok. And how can you implement this?

[nandona]

This seems exactly like Nand

[ivant]

Not NAND really, but quite close. Look at the other gates that you've implemented.

[nandona]

Opposite of Nand, sorry. probably Nand(a=in, b=sel, out=out1); Not(in=out1, out=out); Maybe?

[ivant]

Yes, this is called AND gate. I assume you are doing them in the order described in the book, right?

Ok, now let's create another gate, with the following spec. it again has two inputs: in and sel, and one output out, such that out = in if sel == 0 and 0 if sel == 1.

[nandona]

Oh lol. Ok so this is the table:
in sel out
1 0 1
0 0 0
1 1 0
0 1 0
But I don't know how to implement it to a gate

[ivant]

What if you add another column to the table? It's neither input nor output, just intermediate column to help you. It will contain NOT(sel), the negated value of sel. How would that look like?

It would be more helpful if you order the table like that:

in sel NOT(sel) out
0  1   _        _
1  1   _        _
0  0   _        _
1  0   _        _

[nandona]

This is table I got:
in sel NOT(sel) out
0 1 0 0
1 1 0 0
0 0 1 0
1 0 1 1

this seems like its Not(in=sel, out=nsel);And(a=in, b=nsel, out=out);

[ivant]

Yes, exactly!

Now you have two gates; exposes its in input when sel == 1 and the other one exposes its in when sel == 0. You need to somehow combine them to produce the specification of mux.

[nandona]

Thank you!! I think I figured it out.
This is what I got:
And(a=b, b=sel, out=b1);
Not(in=sel, out=nsel);
And(a=a, b=nsel, out=ar);
Or(a=ar, b=b1, out=out);
so the first one returns b when sel is 1 (not 0)
and the second and return a when sel is 0 (so i does the same thing with the first and but after i changed it to the opposite meaning,1 )
and then the Or statement is to see which one needs to be returned.
if sel was 0
that means that the first and will always return 0 therefore not affecting the last or statement
if sel was 1
then the second and will return 0 therefore not affecting the last or statement
if i got this right, I hope I did

[ivant]

Yes, that is correct. And for these smaller gates the course material includes full tests. So if the tests pass you know it's working correctly.

There are more "mechanical" ways to come up with implementation for this, in the sense that you just follow a few steps and you get the result. You can search for "from truth table to normal form" (DNF and CNF are the two normal forms so you may see this in the results) and for "Karnaugh map" (often abbreviated as K-Maps). Both are good to know, but they are impractical to use for bigger and more complex gates.