Confused on HDL implementation and results

[Schopenhaur1859]

CHIP Not {
    IN in;
    OUT out;

    PARTS:
    Nand(a=true, out=false);
    Nand(b=false, out=true);
   
    }

That is my code and I am getting comparison failure on line 2. I am getting 0, 0. But I believe I should be getting of 0, 1 for my output chart.

If someone could please assist me with my code.

*I had to edit mistakes from original post*

Thank you,

[WBahn]

You need to remember that the file merely describes how parts are connected together.

Think of the part you are defining as a box that has connectors on the side of it -- in this case you have a connector marked 'in' and a connector marked 'out'. What the HDL does is place other parts (each of which is a box possibly containing yet other parts) and connecting wires between the ports on the part you are building to the ports on the parts you've placed inside the box.

Inside this box you have placed two parts. Each of these two boxes have two ports, one marked 'in' and one marked 'out'. To the 'in' port on one box you have connected a signal that forces that port to always be True while on the other part you've connect its 'in' port to a signal that forces that port to always be false. The output port of the first part you've connected to a signal that tries to force it to always be False and, similarly, your trying to force the output of the other part to always be True. Think of the True and False signals as the outputs of two power supplies, the first of which is always set to a high voltage and the second is always set to zero volts. You are connecting two outputs together -- the result is known as "contention" and the behavior is undefined.

In addition, you have not connected the 'in' or the 'out' ports of your main box to anything at all.

Finally, consider what's inside the two boxes within your main box. Two Not gates. But what's inside those boxes? Two more Not gates. And inside each of those is two more Not gates. This is known as recursion and it is like standing between two mirrors that are facing each other -- you have infinite reflections. You could never actually build the thing.

Look carefully at the HDL for the Xor chip in Figure 1.6 and see how it matches up to the schematic above it. Now see what happens if you try to draw the schematic that matches your HDL code.

Then consider the behavior of a single Nand gate. If you tie one input to a permanent False, what is the output in terms of the other input? If, instead, you tie one input to a permanent True, what is the output in terms of the other input? Does either of these have a useful behavior if you are trying to get something to behave like a Not gate?

[ivant]

What chip are you trying to implement? You cannot implement a chip using itself (directly as your code shows, or indirectly, through another chip).

[Schopenhaur1859]

I am doing the first assignment 01 and am working on the first chip. The Not chip.

[Schopenhaur1859]

I posted the wrong HDL code. I have posted the correct one. Can you assist me with this one?

[WBahn]

Schopenhaur1859 wrote

I posted the wrong HDL code. I have posted the correct one. Can you assist me with this one?

Although you no longer have a recursion issue, all of the others remain.

Remember what the HDL code represents -- you have two Nand gates, each of which have two inputs ('a' and 'b') and one output ('out'). Your HDL defines how those gates are hooked up, both to each other and to the input and output ports of the new part you are constructing.

Think of an eco-friendly bathroom module in box containing a sink, a toilet, and a tank. This module has two connections -- 'in' and 'out'. We will connect a fresh water supply to the 'in' and the sewer line to the 'out'. Inside we have the three parts. The sink and toilet have 'in' and 'drain' ports while the tank has two input ports named 'white' and 'grey' and a single output port named 'out'.

The idea is that fresh water comes into the module and goes to the sink. After it leaves the sink it is considered 'grey water' and goes to the tank. The toilet is fed from the tank's output port. Because there may not be enough grey water in the tank to operate the toilet, the tank also has an input port for fresh water that it can use if necessary.

Our HDL for this might look like

CHIP Bathroom {
   IN in;
   OUT out;

   PARTS:
   Toilet(in = greyWater2, drain = out);
   Tank(grey = greyWater1, white = in, out = greyWater2);
   Sink(in = in; drain = greyWater1);
   }

Try to draw a picture of this set up.

I also again refer you to Figure 1.6.