Appendix A (pdf) is available on the nand2tetris site. Section A.5.3 is about buses.
Also see 
Hardware Construction Survival Kit sections 
Bit Numbering and Bus Syntaxand 
Sub-busing.
I assume that you are working on Not16. You need to treat Not16's 
in and 
out as 16 pairs of individual wires named "in[0]", "out[0]", "in[1]", etc.
--Mark