Different bus widths in ALU chip

[Sftware_learner]

I am currently doing 8-bit ALU chip, and also creating my own chip named mult.
I tend to use it as multiplying the value of x & y, however, as I run my ALU chips, it showed up that my chips have different bus widths.

螢幕快照_2018-11-25_15.png
螢幕快照_2018-11-25_15.png
螢幕快照_2018-11-25_15.png
螢幕快照_2018-11-25_15.png

Basically, what I would like to do for the chip is to use it to multiply x & y value & also test its overflow.
My problem is that I still could not run this part successfully due to some small issues.
Hope that someone could point out where my problem is.

[xedover]

The first problem I see is that many of your Mux16 b inputs aren't connected to anything, because there's a space between the equal and the wire name (b= shift1 --> should be --> b=shift1 (no space))

We can't see the chip definitions for your other chips, so we don't know their bus width. Is your Shift chip a single bit or 16-bit? Is your Overflow chip a single bit or 16-bit?

You have the output of each of your Overflow chips connected to the output of each of your Mux16's. Is this your intent? It doesn't seem correct.

And finally, I don't see anything connected to your chip's out[16] wire, at all. None of your chip's outputs are connected to anything going out.

Have you tried diagramming out the logic circuit? Its not entirely clear what this chip is supposed to do. I suggest drawing out your logic circuit diagram on paper to see how all the parts are supposed to connect to each other. See for example my diagram of an Xor chip here: http://nand2tetris-questions-and-answers-forum.32033.n3.nabble.com/Visual-Chip-Implementation-XOR-gate-example-td4032559.html

Hope this helps