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wudi8913 wrote
I need help with this software, I built and tested my NOT gate. Its all good.
When I try to test my And gate, i got this error(failure at line 5).
No idea what to do now.
Look at your part's output (View: Output). The last line shown is the line that miscompared.
Look at the expected output for that line (View: Compare) and note what's different. For And, there's only one output so only the 'out' column will mismatch.
Look at the 'a' and 'b' input values to know what is to be computed.
Hint: the most common reason for an output to always be 0 is that it is not connected. Make sure that somewhere in your HDL there is a 'something=out' connection.
If you are still stuck, feel free to email me your And.hdl and I can help you more directly.
--Mark
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