FullAdder [ BuiltIn ] Design Type

[rjrotheryjr]

Everyone,

I read that the Kogge–Stone adder is the fastest.

Does anyone know the BuiltIn FullAdder's design type?

Best,
Richard
 

[ybakos]

The one we build in HDL is a ripple-carry adder, for its simplicity.

The built-in is software-driven, and because of this abstraction I don't believe it adheres to a specific adder design.

[cadet1620]

rjrotheryjr wrote

Does anyone know the BuiltIn FullAdder's design type?

ybakos wrote

The one we build in HDL is a ripple-carry adder, for its simplicity.

The built-in is software-driven, and because of this abstraction I don't believe it adheres to a specific adder design.

As Yong wrote, the built-in parts are software (written in Java). Assuming that the Java code does something like io_pins.out = io_pins.a + io_pins.b, it will be using your computer's CPU's addition hardware.

There are some forum posts on faster adder architectures:
    Carry Look-Ahead Adder
    Carry Select Adder
    Carry Bypass Adder

If I remember correctly, Kogge–Stone is a space/time trade-off that optimizes carry-lookahead adders for time.

If you implement it in HDL, please post it to the forum!

--Mark

[rjrotheryjr]

Thank you Yong.

After reviewing Mark's response and the Java source,
you're correct it does not adhere to any specific design.
The java source is the following:

package builtInChips;

import Hack.Gates.BuiltInGate;

/**
 * A FullAdder.
 * s returns the LSB of the sum of the three bits a,b and c.
 * cout returns the carry bit.
 */
public class FullAdder extends BuiltInGate {

    protected void reCompute() {
        short a = inputPins[0].get();
        short b = inputPins[1].get();
        short c = inputPins[2].get();
        short sum = (short)(a + b + c);
        outputPins[0].set((short)(sum % 2));
        outputPins[1].set((short)(sum / 2));
    }
}

Best,
Richard

[rjrotheryjr]

Thanks for the information Mark.

You are correct the Java source is similar to the code you previously posted.
It makes sense to use each user's CPU hardware architecture for the [ BuiltIn ] gates/chips.

If I successfully write a Kogge-Stone implementation, I will certainly post the HDL.


Best,
Richard

[rjrotheryjr]

Hi Mark,

I have added a 16-bit Kogge-Stone Parallel Prefix Adder to the forum at:

Kogge-Stone 16-bit Parallel Prefix Adder

I also included an image and a .circ file.
The HDL successfully tests on my platform.

Best,
Richard