HDL in posts

[Simon van Meygaarden]

Greetings, All!

First question: am I allowed to post HDL implementations on this forum?

When looking at earlier posts I noticed several where HDL was deleted, yet more recent posts still have HDL in them. Furthermore, it makes talking about implementations so much easier if you can simply show the HDL statements.
I have also enrolled in the upcoming Coursera version of this course, which starts on July 31, but I fear on their forums it will not be allowed to post problem solutions, so I am really hoping this forum does allow this.

Take care,
Simon

[ybakos]

Thanks for asking! Please do not post solutions in the forum.

[cadet1620]

Simon van Meygaarden wrote

First question: am I allowed to post HDL implementations on this forum?

When looking at earlier posts I noticed several where HDL was deleted, yet more recent posts still have HDL in them. Furthermore, it makes talking about implementations so much easier if you can simply show the HDL statements.

Yes, it is OK to post your HDL to get help with it. It is easy to edit your post to remove the bulk of the HDL after your problem is solved.  I encourage leaving the broken part of your HDL in the post so that others can learn from it.

For chips that are part of the course, we don't want to have solutions in the forum.

--Mark

[Simon van Meygaarden]

Hai, Yong, Mark, good to meet, and both thanks for the fast reply. -smile-

OK, I'll will try not to post full solutions, and if needed, I'll remove them afterwards. I have no problem with admins editing my posts whenever needed...

Here's a question I can ask without any HDL: the obvious way to create an And16 is duplicate ones And solution 16 times, which would take, in my case, 32 HDL statements. However, one could also create a new Nand16 (taking 16 statements), add a new Not16 (one statement), and then implement the And16 with only 2 statements. That's 19 in total.
But, thinking some further, I could also build a Nand2 (2), then a Nand4 (2), then a Nand8 (2), then a Nand16 (2), then a Not16 (1), and then I can make an And16 (2) with only 11 statements in total.

So obviously, there are a lot of different ways to implement even a simple chip like an And32. My question is: what are the right criteria to optimize ones solution? In the real world, electronically speaking, I would guess speed and power consumption, but within our virtual simulation, power consumption doesn't exist, and I wonder how I can speed up my virtual computer (once, I hope, I build it... -smile-)

Any thoughts would be appreciated...
Simon

[ybakos]

Have fun experimenting with building your own chips! But for these projects, do not worry too much about optimizing the hardware.

[cadet1620]

As you say, there are many parameters that can be optimized in hardware — speed, size, and power consumption for example.  There are the usual tradeoffs.  Simple circuits like ripple-carry adders are slow, but faster adders like carry lookahead are larger and use more power.

I think that the fewer parts in the parts section is generally a good target, but not taken to extreme.
More understandable circuits are better than short, obscure circuits.

You should not write Nand only implementations of the later parts. One of the goals of the nand2tetris course is to get you thinking of high level abstractions. Always think about parts that you have written and tested and how you can use then to make the next part. For example, for And16, use 16 And parts;

The HardwareSimulator does not run fast enough to simulate any but the most basic programs, so don't worry about optimizing its performance. You will be running programs in the CPUEmulator, which emulates the machine language running on the Hack computer designed in chapter 5.

Another great tool for playing with logic circuits is Logisim. Powerful enough to build a Hack computer.

--Mark

[Simon van Meygaarden]

Mark;

I understand the abstraction paradigm, don't worry, but I am just trying to get the most out of the learning experience (as well as having a whole lot of fun -smile-), and I just wondered about the purpose of the exercises.
For example, working in sequence, after the DMux I tried the Not16, as a simple 16 Nots (16 statements). Then I realized that a simple And16 made from 16 Ands would take 32 statements, and a Or16 from 16 Ors would take 48 statements. It would surely work, but it felt a waste of time, which couldn't be the purpose of the exercise, so I tried something else.
Another example: for the Mux16 I needed two And16s with 16-bit select input, and specifying each select individually (b[0]=sel, b[1]=sel, etc.) seemed a waste of time. So I created a repeater using a Nop (single input Nand + Not), multiplied that to Nop16, and then used two Nop16 to provide the 16-bit select for the And16s. (Hope this makes sense without HDL... -smile-)
In any case, thanks for the link to Logisim, I'll check that out tomorrow.

Take care,
Simon

[cadet1620]

For what it's worth, I called my 1-1 connection Wire and my 1-16 expander Bus16.

Also, keep multiplexors in mind; they do much more than just data selection. For example, the entire instruction decoding for the CPU can be done with one Mux16.

Also, to save typing I wrote an HDL preprocessor. It saved a lot of typing generating the HDL for the 1160 Nand gate CPU.

--Mark

[Simon van Meygaarden]

LOL - I thought about Bus, but reserved that for a 4-1 concentrator, to save 4 Or's...

Seriously, yesterday evening I finally watched the chapter 01 lectures on YouTube, and that answered a lot of my questions about optimal solutions. However, I am still left with a bit of an uneasy feeling.

Now, I am sixty years old, I have 30 years experience in ICT, with an additional physics and electronics background, so I am probably both old-fashioned and not really part of the target audience; and I do understand the huge advantage of self-learning, practice, and the probably unique test-driven educational experience this course offers; but I still lack the feedback of contemporary education to get an insight into the expected solution of a problem, once you tried it yourself.

Most obvious example: I wrote my Mux4Way16 with only Nots, Ands/And16s and Ors, adding a 1-16 expander I wrote myself. It passed validation, I was happy, and if it wasn't for this forum, I would have never thought about using 3 Mux16's and a 4-bit decoder.

So here's an idea: if there is still active development on the Hardware Simulator, why not add a pop-up dialog that shows you the preferred solution of particular chip (the one used to create the compare file) ONLY when your own solution of that particular chip passes validation. In other words, change the message:

        End of script - Comparison ended successfully

to

        End of script - Comparison ended successfully - press s to see our implementation

The pop-up dialog could only display HDL, but it could also have additional comments and such.

This would not change the basic test-driven system, it would not spoil anything, because you don't get the pop-up if your validation fails, and it would add an additional level of feedback, which, in my humble experience, could be vary valuable.

Any thoughts?
Simon